안녕하세요
하기와 같은 논문의 대한 파형을 Spectre에서
구현해보고 싶습니다. 1차에서 5차까지
(First through fifth harmonic output power as a function of input power simulatedl
CMOS technology with a gate width of 5um and a gate length of 0.3um. Dashed lines indicate the theoretical slopes. In this two-tone
intermodulation distortion simulation (1.8 GHz, 1.9 GHz), the device was operated in common-gate configuration with 50ohm at the input and 50 ohm at
the output and with Vds=1V and Vds=Vsb=0V)
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4907311
상기 IEEE 논문의 Fig.11 재현방법 문의